Chapter 05. SH3's architecture
・embedded RISC microprocessor
・16-bit fixed length instruction and 5-stage pipeline
3rd gernation in SuperH family
When a interrupt occurs SH3 jumps to a fixed address and goes to braches arranged by software, in contrast to the use of interrupt vector table in SH1 and SH2.
・SH3＋X/Y memory＋DSP module
・In ASP kernel, the internal timer（ＴＭＵ0） and the external SIO （ST16C2550CQ48） are used as kernel's SYSLOG output.
It has two kinds, one is called supervisor mode and the other is user mode. In ASP, both the kernel and the tasks are running in supervisor mode, as has been explained in Chapter 3. CPU mode can been changed by setting the MD bit of the status register (SR). In the ASP kernel, SR.MD is always 1 (1: supervisor mode, 2: user mode)
Next we give an introduction of the registers of SH3
General-purpose Registers: R0〜R15 （R0_BANK0〜R7_BANK0,R0_BANK1〜R7_BANK1，R8〜R15）
Control Registers: GBR,SR，SSR,SPC
System Registers: MACH/MACL,RP（holding the return address）,PC（program counter）
There are 16 general-purpose registers, designated as R0 to R15, with R0 to R7 each having two register banks, BANK0 and BANK1.
Figure 5-1 CPU registers
Each of R0~R7 has two physical registers, only either of which is visible at one time. RB bit of the status register determines which one is visible.
For example, any attempt to access r0 in the program is actually to access either bank's R0, and which one to access depends on the value of RB bit. If RB = 0, BANK0 is visible; if RB = 1, then BANK1. R0 of the invisible bank can be accessed by using r0_bank explicitly.
In the ASP kernel, this mechanism is made use of at the interrupt entry, which speeds up the interrupt processes. In general, to obtain the work area for the interrupt process, we need to store/load the general-purpose registers. But in the case of SH, with the register bank function, hardware itself conducts storing/loading, which reduces the overhead in software.
Registers arrangement for GNU Compiler
SH3 does not prepare an exclusive register for the stack pointer. Any general-purpose register can be used as a stack pointer. In the case of GNU compiler, R15 is specified. The register assignment is shown below:
R0：a function's return return value
normally it is unnecessary for a called function to backup them. If really necessay , programmers need to do the backup themselves.
R4-R7：parameter; parameters over 5 are accumulated into the stack.
R8-R13：registers that are required to be backuped by a called function.
If used in a called function, they should be stored.
・R8〜R13: necessary for the called function to backup (callee-saved register)
Status register is comprised of several flag bits representing CPU status. These flag bits are operation mode switching bit (MD), block bit for exception disabling, currently-used bank bit (RB), condition branch bit (T) and 4 bits (I) for 15-level interrupt mask.
processing mode bit
fixed to 1 in ASP for always in supervisor mode.
register bank bit
inicates which bank to use.
if 1, the general-purpose registers are R0_BANK1〜R7_BANK1 R8〜R15.
if 0, the general-purpose registers are R0_BANK0〜R7_BANK0 R8〜R15.
when any interrupt occurs, it is set to 1 automatically and then BANK1 is visible.
if 1, blocks exceptions and interrupts.
if any exception occurs when BL = 1, the reset is triggered. it cannot be used for interrupt-disabling.
interrupt mask bit
4 bits, representing the interrupt levels.
the larger the value is, the higher the priority is. when it is 1111, the maximum value, any interrupt will not be accepted, in the other word, interrupts is disabled.
flag for branches.
it determines whether to branch.
GBR：Global Base Register
holds the base address in indirect addressing.
VBR：Vector Base Register
when any interrupt occurs, program jumps to a fixed address, which is held by this register. Program can jump to anywhere by modifying its value.
SPC：Saved Program Counter (Saved PC)
saves the return address (PC) when any exception occurs.
SSR：Saved Status register (Saved SR)
saves SR when any exception occurs.
- system register
holds the currently executed memory address.
saves the return address (PC + 2) when program branches to a subroutine procedure. it is used in the case of function calls and so on.
Sequence of an Exception Processing
The processor will begin the following actions when an exception happens during program execution.
・stores PC into SPCYou should note that RB bit has been set to 1 by the proccessor at this point.
・stores SR into SSR
・disables interrupts （SR．BL = 1），shifts to the supervisor mode （SR.MD = 1）
・switches R0〜R7 to BANK１ （SR.RB = 1）
・executes the exception handle routine
Exception Handling Vector Address
internal error VBR + 100h
TLB miss VBR + 400h
NMI, external hardware interrupt VBR + 600h
It can be concluded that program execution will start at the address VBR＋600 when an interrupt is generated. The ASP kernel places at here the program executed when interrupts happen .
Return from Exception Handling
The RTE instruction is used to return execution from exception processing. When RTE is executed,
・the SPC value is set in the PC
・the SSR value is set in the SR
At the exception handler entry routine, values stored in the SPC and SSR are set back to the PC and the SR.
At the exception handler exit routine, RTE is executed.
Registers Related to Exceptions
The interrupt handler entry routine placed at VBR+H'600 confirms which interrupt has happend. The interrupt event register contains an interrupt exception code, set when an interrupt occurs depending on the interrupt source, which can be used for software to judge the interrupt source.
interrupt event register （INTEVT）
interrupt event register 2 （INTEVT2）
The interrupt cause is set when an interrupt is generated.
We use INTEVT2 at SH727.
- processor interrupt priority mask (IPM)
The bits 7 to 4 of the SR are set with the interrupt priority.
- interrupt priorities
Interrupt Priority Registers A to G （IPRA〜IPRG） are set with the priority of the correspondent interrupts.
Which bits of which register will be set depends on the interrupt source.
- interrupt causes
Interrupt causes, wrriten to interrupt event register 2 (INTEVT2) after the acceptance of any interrupt, are used to identify interrupt events.
Interrupt processing flow
We conclude the actions taken by the processor when an interrupt happens:
・ stores PC to SPC, and SR to SSRNested Interrupts
・ sets the BL bit of the SR to 1 to have all exceptions blocked.
・ set sthe MD bit of the SR to 1 and shifts to the supervisor mode. (In the ASP kernel, tasks and interrupt handlers run in the supervisor mode)
・ sets the RB bit of the SR to 1 to used registers bank 1.
・ writes the exception cause to the correspondent bit of INTEVT and INTEVT 2. (In the ASP kernel, INTEVT 2 is used.)
・ executes the exception routine from the address VBR+0x600.
We have made it clear that when an interruts occurs, the processor will take actions, as is listed up above.
It is an important thing that the other interrupt can be accepted during execution of one interrupt handler if realtime performance is required. In the ASP kernel, the following actions are taken for the inplementation of nested interrupts before enabling interrupts. (It is not the processor but the kernel who conducts these actions. )
・sets the priority of the current interrupt to SR.I3-I0
It is not necessary to accept an interrupt with the lower priority than the interrupt being handled. Therefore the interrupt priority of the processor should be set with the priority that the accepted interrupt is holding.
・stores the SSR and SSC
The contents of SSR and SSC will be overwritten automatically when another interrupt is accepted so backup is necessary.
・clears the BL bit
Then, the interrupt with higher priority can be accepted.
What we have explained in this chapter is concluded in the following chart.
Figure 5-2 flow when an interrupt happens
Actions conducted by the processor and those by the kernel should be distinguished.
We will describe the interrupt-related routins in the kernel later on.